05131081 is referenced by 58 patents and cites 16 patents.

An input/output (I/O) processor and data processing system in which the processor receives and services interrupt request signals from I/O controllers, which requests may be internally or externally coded, and supervises blockwise transfer of data between an external memory associated with a main processing unit and the I/O controllers. The I/O processor includes an internal memory for storing information pertinent to data transfer from each I/O channel including the address where channel programs, decision tables and data buffers are maintained in external memory. A sequencer executes a specialized instruction set which includes instructions that invoke an interpretation means enabling examination of status registers of the I/O controllers and/or data values therefrom and the branching of execution based thereon. The I/O processor and I/O controllers may be interconnected with a local external memory via a local bus which is selectively coupled with a system bus interconnecting the main processor unit and main external memory.

Title
System having a host independent input/output processor for controlling data transfer between a memory and a plurality of I/O controllers
Application Number
7/327845
Publication Number
5131081
Application Date
March 23, 1989
Publication Date
July 14, 1992
Inventor
Cecil H Kaplinsky
Palo Alto
CA, US
Craig A MacKenna
Los Gatos
CA, US
Agent
Jack D Slobod
Assignee
North American Philips Corp Signetics Div
CA, US
IPC
G06F 13/10
G06F 13/12
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