05130568 is referenced by 113 patents and cites 19 patents.

A scannable latch system comprises a plurality of scannable latches and clock driver circuit that allow at-speed testing of integrated circuits. Each scannable latch comprises a master latch, a slave latch and an auxiliary latch. The master latch is a two input latch capable of receiving data from two sources. The output of the master latch is coupled to the input of the slave and auxiliary latches. The clock driver circuitry receives a clock and control signals which are transformed into signals that operate the scannable latch in three different modes. In the normal mode, the slave latch is transparent and the data is held primarily in the master latch. In the scan mode, data may be shifted into the master, shifted out through the auxiliary latch, or shifted both in and out with a propagate function. Finally, in a test mode independent data values may be stored in the master latch and the slave latch.

Title
Scannable latch system and method
Application Number
7/609398
Publication Number
5130568
Application Date
November 5, 1990
Publication Date
July 14, 1992
Inventor
Laurence H Cooke
San Jose
CA, US
William W Walker
Los Gatos
CA, US
Brent W Miller
Menlo Park
CA, US
Agent
Greg T Sueoka
A C Smith
Assignee
Vertex Semiconductor Corporation
CA, US
IPC
H03K 3/286
H03K 3/289
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