05129067 is referenced by 220 patents and cites 5 patents.

A multiple instruction decoder includes an input latch for receiving a plurality of logic instructions, wherein the plurality of logic instructions include N register-operand identifiers; arbitration logic coupled to the input latch for arbitrating read port contentions by the N register-operand identifiers for M available read ports (where M is less than N) based on arbitration data corresponding to each of the logic instructions, and for generating control signals indicative thereof; and a multiplexing unit for selectively supplying the N register-operand identifiers to the M available read ports in response to the control signals generated by the arbitration logic.

Title
Multiple instruction decoder for minimizing register port requirements
Application Number
7/361914
Publication Number
5129067
Application Date
June 6, 1989
Publication Date
July 7, 1992
Inventor
William M Johnson
San Jose
CA, US
Agent
Foley & Lardner
Assignee
Advanced Micro Devices
TX, US
IPC
G06F 12/02
G06F 9/38
G06F 9/34
G06F 9/30
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