05125083 is referenced by 73 patents and cites 16 patents.

An operand processing unit delivers a specified address and at least one read/write signal in response to an instruction being a source of destination operand, and delivers the source operand to an execution unit in response to completion of the preprocessing. The execution unit receives the source operand, executes it and delivers the resultant data to memory. A "write queue" receives the write addresses of the destination operands from the operand processing unit, stores the write addresses, and delivers the stored preselected addresses to memory in response to receiving the resultant data corresponding to the preselected address. The addresses of the source operand is compared to the write addresses stored in the write queue, and the operand processing unit is stalled whenever at least one of the write addresses in the write queue is equivalent to the read address. Therefore, fetching of the operand is delayed until the corresponding resultant data has been delivered by the execution unit.

Title
Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system
Application Number
7/306767
Publication Number
5125083
Application Date
February 3, 1989
Publication Date
June 23, 1992
Inventor
Jr David A Webb
Berlin
MA, US
John E Murray
Acton
MA, US
Ricky C Hetherington
Northboro
MA, US
Tryggve Fossum
Northboro
MA, US
David B Fite
Northboro
MA, US
Agent
Arnold White & Durkee
Assignee
Digital Equipment Corporation
MA, US
IPC
G06F 9/312
G06F 9/30
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