05123095 is referenced by 87 patents and cites 11 patents.

A vector processor is closely integrated with a scalar processor. The scalar processor provides virtual-to-physical memory translation for both scalar and vector operations. In vector operations, a block move operation preformed by the scalar processor is intercepted, the write command in the operation is converted to a read, and data resulting from a vector operation is returned to the address specified by the block move write command. Writing of the data may be masked by a prior vector operation. Prefetch queues and write queues are provided between main memory and the vector processor. A microinstruction interface is supported for the vector processor.

Title
Integrated scalar and vector processors with vector addressing by the scalar processor
Application Number
7/297981
Publication Number
5123095
Application Date
January 17, 1989
Publication Date
June 16, 1992
Inventor
James T Pinkerton
Newton
MA, US
David E Culler
Boston
MA, US
Gregory M Papadopoulos
Arlington
MA, US
Agent
Hamilton Brook Smith and Reynolds
Assignee
Ergo Computing
MA, US
IPC
G06F 15/347
View Original Source