05120671 is referenced by 48 patents and cites 4 patents.

A method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device. This method and apparatus allows reduced memory cell size and improved device density by substantially eliminating the bird's beak encroachment and corner rounding effects usually found between neighboring cells due to inadequacies in the prior art photolithography process. This method and apparatus is particularly appropriate for use with EPROM, Flash EPROM, EEPROM, or other types of memory cells and in periphery devices.

Title
Process for self aligning a source region with a field oxide region and a polysilicon gate
Application Number
7/621284
Publication Number
5120671
Application Date
November 29, 1990
Publication Date
June 9, 1992
Inventor
Wen Juei Lu
Sunnyvale
CA, US
Daniel N Tang
San Jose
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
H01L 21/76
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