05120670 is referenced by 27 patents and cites 6 patents.

The present invention provides a method of fabricating a virtual ground EPROM cell in a silicon substrate of P-type conductivity. In accordance with the method, a gate oxide layer is formed on the silicon substrate. This is followed by the formation of a first layer of polysilicon (poly 1). Next, a composite structure comprising oxide-nitride-oxide (ONO) is formed on the first polysilicon layer. Next, a photoresist mask is used to define parallel lines of ONO/poly 1. After etching the ONO/poly 1 to define the parallel lines, an arsenic implant is performed while keeping the photoresist mask in place to define N+ bit lines between the lines of ONO/poly 1. After the photoresist is stripped from the parallel lines of ONO/poly 1, an oxidation step is performed to complete the oxidation of the ONO and to simultaneously grow a differential oxide between the lines of ONO/poly 1. In the subsequent etching of the ONO/poly 1 lines in a stacked etch procedure, the differential oxide overlying the N+ bit lines protects the underlying substrate, thus avoiding interruption ("digging") of N+ bit lines in the EPROM array.

Title
Thermal process for implementing the planarization inherent to stacked etch in virtual ground EPROM memories
Application Number
7/687106
Publication Number
5120670
Application Date
April 18, 1991
Publication Date
June 9, 1992
Inventor
Albert M Bergmont
San Jose
CA, US
Agent
Limbach & Limbach
Assignee
National Semiconductor Corporation
CA, US
IPC
H01L 21/311
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