05119485 is referenced by 166 patents and cites 13 patents.

A bus snoop control method for maintaining coherency between a write-back cache and main memory during memory accesses by an alternate bus master. The method and apparatus incorporates an option to source `dirty` or altered data from the write-back cache to the alternate bus master during a memory read operation, and simultaneously invalidate `dirty` or altered data from the write-back cache. The method minimizes the number of cache accesses required to maintain coherency between the cache and main memory during page-out/page-in sequences initiated by the alternate bus master, thereby improving system performance.

Title
Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation
Application Number
7/351898
Publication Number
5119485
Application Date
May 15, 1989
Publication Date
June 2, 1992
Inventor
Russell A Reininger
Austin
TX, US
William B Ledbetter Jr
Austin
TX, US
Agent
Robert L King
Assignee
Motorola
IL, US
IPC
G06F 12/08
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