05117486 is referenced by 55 patents and cites 12 patents.

A bus-to-bus adapter is provided for coupling the input/output bus of a first data processor to the input/output bus of a second and different type of data processor. The adapter enables the transfer of data and messages from the first processor to the second processor and vice versa. The adapter includes a buffer storage unit and control logic for enabling multiple data buffers to be provided for enabling multiple independent data transfer operations to be performed in a concurrent manner. The control logic also includes a mechanism for allowing the reading out of data from a data buffer to begin before such data buffer has received all of its incoming data. The adapter further includes a programmable service time allocation mechanism for limiting message service time relative to data transfer service time and for providing different amounts of data transfer service time for different ones of the multiple data buffers.

Title
Buffer for packetizing block of data with different sizes and rates received from first processor before transferring to second processor
Application Number
7/341503
Publication Number
5117486
Application Date
April 21, 1989
Publication Date
May 26, 1992
Inventor
James W Valashinas
Endicott
NY, US
James E Hughes
Hallstead
PA, US
Joseph P Higham
Endicot
NY, US
Alan R Clark
Endicot
NY, US
Agent
Arthur J Samodovitz
Richard E Bee
Assignee
International Business Machines
NY, US
IPC
G06F 13/00
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