05115510 is referenced by 83 patents and cites 15 patents.

An information processor includes a program memory for storing a data flow program having destination information and instruction information as one set. Destination information, instruction information and operand data included in an input data packet are latched in an input data latching portion. Only the operand data is transferred to an output data latching portion. An address is operated based on the destination information latched in the input data latching portion, and the program memory is accessed, so that the data flow program is read out. The destination information and the instruction information included in the read data flow program are latched in the output data latching portion. Paired data is detected by a paired data detection portion based on the data flow program latched in the output data latching portion. The detected data is operated by an operation processing portion.

Title
Multistage data flow processor with instruction packet, fetch, storage transmission and address generation controlled by destination information
Application Number
7/259722
Publication Number
5115510
Application Date
October 19, 1988
Publication Date
May 19, 1992
Inventor
Souichi Miyata
Nara
JP
Toshiya Okamoto
Kyoto
JP
Assignee
Sharp Kabushiki Kaisha
JP
IPC
G06F 3/00
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