05115411 is referenced by 22 patents and cites 14 patents.

A system comprising a memory for transferring m data bytes at a time, first and second busses each having a width of less than m data bytes, first parallel m byte wide read and write registers connected between the first bus and the memory and second parallel m byte wide read and write registers connected between the second bus and the memory.

Title
Dual port memory system
Application Number
7/534081
Publication Number
5115411
Application Date
June 6, 1990
Publication Date
May 19, 1992
Inventor
Michael R Hilley
Belton
SC, US
William J Kass
Easley
SC, US
Agent
Douglas S Foote
Assignee
NCR Corporation
OH, US
IPC
G11C 11/409
G11C 11/407
G11C 7/00
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