05111413 is referenced by 177 patents and cites 12 patents.

A simulation system for circuit design is disclosed. The system couples a schematic editor and simulator to allow incremental changes to a design under test without requiring prior shutdown of the simulator. The system uses a method which permits a wide range of changes to the design and provides a resulting netlist for the changed design. Changes can be made to the schematic which include changes in hierarchy, addition or deletion of components (including hierarchical components), addition or deletion of signals at any level within the design hierarchy, addition or deletion of interconnections of components at any level of hierarchy within the design, addition and deletion of interface ports for any component type, substitution of a new component for an existing one (including swapping hierarchical and behavioral descriptions), and alteration of parametric data such as device delay timing. The simulation continues to run after design changes are made. The method may be used in conjunction with hardware modeling systems.

Title
Computer-aided engineering
Application Number
7/328427
Publication Number
5111413
Application Date
March 24, 1989
Publication Date
May 5, 1992
Inventor
Alec G Stanculescu
San Mateo
CA, US
Kenneth E Scott
Fremont
CA, US
David R Coelho
Fremont
CA, US
Thomas R Miller
Palo Alto
CA, US
Richard W Lazansky
Pleasanton
CA, US
Agent
Townsend and Townsend
Assignee
Vantage Analysis Systems
CA, US
IPC
G06F 15/20
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