05104820 is referenced by 250 patents and cites 5 patents.

A process is disclosed which applies advanced concepts of Z-technology to the field of dense electronic packages. Starting with standard chip-containing silicon wafers, modification procedures are followed which create IC chips having second level metal conductors on top of passivation (which covers the original silicon and its aluminum or other metallization). The metal of the second level conductors is different from, and functions better for electrical conduction, than the metallization included in the IC circuitry. The modified chips are cut from the wafers, and then stacked to form multi-layer IC devices. A stack has one or more access planes. After stacking, and before applying metallization on the access plane, a selective etching step removes any aluminum (or other material) which might interfere with the metallization formed on the access plane. Metal terminal pads are formed in contact with the terminals of the second level conductors on the stacked chips. The pads and terminals are formed of the same metallic material in order to maximize T-connection conducting efficiency.

Title
Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting
Application Number
377241
Publication Number
5104820
Application Date
June 24, 1991
Publication Date
April 14, 1992
Inventor
Stuart N Shanken
Laguna Niguel
CA, US
Joseph A Minahan
Simi Valley
CA, US
Tiong C Go deceased
late of El Toro
CA, US
Agent
Thomas J Plante
Assignee
Irvine Sensors Corporation
CA, US
IPC
H01L 21/60
H01L 21/58
H01L 21/56
H01L 21/52
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