05101341 is referenced by 111 patents and cites 36 patents.

A system and technique for providing early decoding of complex instructions in a pipelined processor uses a programmed logic array to decode instruction segments and loads both the instruction bits and the associated predecoded bits into a FIFO buffer to accumulate a plurality of such entries. Meanwhile, an operand execute pipeline retrieves such entries from the FIFO buffer as needed, using the predecoded instruction bits to rapidly decode and execute the instructions at rates determined by the instructions themselves. Delays due to cache misses are substantially or entirely masked, as the instructions and associated predecoded bits are loaded into the FIFO buffer more rapidly than they are retrieved from it, except during cache misses. A method is described for increasing the effective speed of executing a three operand construct. Another method is disclosed for increasing the effective speed of executing a loop containing a branch instruction by scanning the predecoded bits in establishing a link between successive instructions.

Title
Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
Application Number
236449
Publication Number
5101341
Application Date
September 2, 1988
Publication Date
March 31, 1992
Inventor
Ralph H Olson
Scottsdale
AZ, US
Roger W Luce
Phoenix
AZ, US
Richard H Duerden
Scottsdale
AZ, US
Joseph C Circello
Phoenix
AZ, US
Agent
Cahill Sutton & Thomas
Assignee
Edgcore Technology
AZ, US
IPC
G06F 9/38
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