The combination of the signed digit (SD) and the logarithmic number system (LNS) for the creation of a hybrid SD/LNS processor. An optimal radix was chosen for the SD system by taking into account both the speed of operations and the memory storage requirements. A technique for parallel converison of SD to sign-magnitude numbers is disclosed. The optimal-SD-radix hybrid LNS processor exploits the parallelism that is offered by the SD number system, and exhibits efficient overflow detection mechanism. It is at least 10 gate delays faster per each LNS addition/subtraction than state-of-the-art traditional LNS processor designs and 8 gate delays faster per each LNS multiplication/division. The gain in speed is achieved at the expense of some small PLAs that have to be included in the design and a small degree of additional complexity of the circuitry.