05091769 is referenced by 105 patents and cites 17 patents.

Packaging methods and configurations are disclosed for placing electronic integrated circuit chips into operable chip systems in a manner to facilitate burn-in and testability thereof. The invention addresses the problem of testing bare integrated circuit chips before they are committed to a multichip module. Further, it addresses the problem of burning-in bare chips under biased conditions so that chips with defects therein can be accelerated to failure, thereby avoiding their incorporation into a multichip integrated circuit module. Pursuant to the invention, special connection arrays are disposed in spacer blocks in a predetermined configuration on a substrate. The blocks define areas of the substrate which preferably accommodate a plurality of integrated circuit chips such that each chip is surrounded on each side by a spacer block. One or more connection arrays may be provided in each spacer block. The connection arrays have interconnection pads which in the final structure are accessible to an external probing device. Specific methods of fabrication are also disclosed.

Title
Configuration for testing and burn-in of integrated circuit chips
Application Number
7/676206
Publication Number
5091769
Application Date
March 27, 1991
Publication Date
February 25, 1992
Inventor
Charles W Eichelberger
1256 Waverly Pl., Schenectady, 12308
NY, US
Agent
Heslin & Rothenberg
IPC
H01L 23/28
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