05089993 is referenced by 62 patents and cites 6 patents.

A semiconductor memory architecture, which includes a given number of discrete components, provides a memory module of increased capacity. The memory module includes a plurality of discrete data memory circuits each organized to provide an individual data string having a length that is an integer multiple of four bits. The data memory circuits are arranged to provide a combined data string having a length equal to the sum of the individual data string lengths. Each data memory circuit includes a signal line connected to control transfer of individual data strings. A different data pin is associated with each bit of the combined data string to transfer a datum for output from the memory module. Each signal line is connected to a control pin to receive an external signal for initiating transfer of one of the individual strings from one of the data memory circuits. The module further includes an additional memory circuit having a plurality of additional signal lines and a plurality of additional data lines. A first of the additional signal lines is wired in common with the signal line of a first one of the data memory circuits. A second of the additional signal lines is wired in common with the signal line of a second one of the data memory circuits. The additional memory circuit is responsive to transfer a bit of data along one of the additional data lines when an individual data string is transferred from one of the data memory circuits.

Title
Memory module arranged for data and parity bits
Application Number
7/415074
Publication Number
5089993
Application Date
September 29, 1989
Publication Date
February 18, 1992
Inventor
Kenneth A Poteet
Houston
TX, US
Joseph H Neal
Missouri City
TX, US
Agent
Richard B Havill
Lawrence J Bassuk
Richard L Donaldson
Assignee
Texas Instruments Incorporated
TX, US
IPC
G11C 11/34
G11C 5/06
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