05084824 is referenced by 144 patents and cites 7 patents.

A design layout sequence for an application specific integrated circuit such as an ECL gate array includes a schematic capture step, which results in a logic netlist file, and a placement and routing step which results in a number of various files defining, for example bias drivers, I/O macros, and relationships between chip pads and I/O signals. The design layout sequence culminates in a physical data base file. To ensure a functional design, the designer's work is simulated after both schematic capture and placement and routing using a library containing simulation models for each type of macrocell used in the design. The gate-level netlist component of the simulation models are created automatically in a computer-implemented technique that identifies each root in the combinatorial circuit, assigns each a logical value, and traverses the tree that originates from each identified root. As each tree is traversed, Boolean equations identifying the logical values at each node encountered are determined in accordance with a set of relationships pertinent to the standard circuit elements and a set of logic value assignment definitions. The resulting set of Boolean equations is used to construct the gate-level netlist that is incorporated into the simulation model of the macrocell.

Title
Simulation model generation from a physical data base of a combinatorial circuit
Application Number
7/502581
Publication Number
5084824
Application Date
March 29, 1990
Publication Date
January 28, 1992
Inventor
Amrit K Lalchandani
Sunnyvale
CA, US
Nim C Lam
Sunnyvale
CA, US
Agent
Skjerven Morrill MacPherson Franklin & Friel
Assignee
National Semiconductor Corporation
CA, US
IPC
G06F 15/60
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