05077691 is referenced by 218 patents and cites 4 patents.

A flash EEPROM cell array is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell and a relatively low positive voltage to the source region of the cell. Because of a relatively low reverse voltage developed between the source region of the cell and the bulk substrate, the generation of hot holes is inhibited and improved performance may be obtained. The source region is preferably single diffused rather than double-diffused so that the cell can occupy a minimum area for a given design rule. The low positive voltage applied to the source is preferably less than or equal to the voltage, V.sub.CC presented at a +5V chip power supply pin. This makes it possible for the +5V pin to directly supply source current during erasure.

Title
Flash EEPROM array with negative gate voltage erase operation
Application Number
7/426332
Publication Number
5077691
Application Date
October 23, 1989
Publication Date
December 31, 1991
Inventor
Michael A Van Buskirk
San Jose
CA, US
Antonio Matalvo
San Francisco
CA, US
Chi Chang
Redwood City
CA, US
Sameer S Haddad
San Jose
CA, US
Agent
Skjerven Morrill MacPherson Franklin & Friel
Assignee
Advanced Micro Devices
CA, US
IPC
G11C 11/40
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