05070032 is referenced by 571 patents and cites 7 patents.

An improved electrically erasable and programmable read only memory (EEprom) structure and processes of making it which results in a denser integrated circuit, improved operation and extended lifetime. In order to eliminate certain ill effects resulting from tolerances which must be allowed for registration of masks used in successive steps in forming the semiconductor structures, spacers are formed with reference to the position of existing elements in order to form floating gates and define small areas of these gates where, in a controlled fashion, a tunnel erase dielectric is formed. Alternatively, a polysilicon strip conductor is separated into separate control gates by a series of etching steps that includes an anisotropic etch of boundary oxide layers to define the area of the control gates that are coupled to the erase gate through an erase dielectric. In either case, the polysilicon layer strip can alternatively be separated by growing oxide thereon until it is completely consumed. A technique for forming a pure oxide dielectric layer of uniform thickness includes depositing a thin layer of an undoped polysilicon material and then oxidizing its surface until substantially the entire undoped polysilicon layer is consumed and made part of the resulting oxide layer. Overlapping doped regions are provided in the substrate by an ion implantation mask that adds spacers to the mask aperture to change its size between implants.

Title
Method of making dense flash EEprom semiconductor memory structures
Application Number
7/323779
Publication Number
5070032
Application Date
March 15, 1989
Publication Date
December 3, 1991
Inventor
Eliyahou Harari
Los Gatos
CA, US
Jack H Yuan
Cupertino
CA, US
Agent
Majestic Parsons Siebert & Hsue
Assignee
SunDisk Corporation
CA, US
IPC
H01L 21/265
View Original Source