05067078 is referenced by 45 patents and cites 8 patents.

A first processing system is coupled to a plurality of integrated circuits along a P bus. Each of these integrated circuits has a combination cache and memory management unit (MMU). The cache/MMU integrated circuits are also connected to a main memory via an M bus. A second processing system is also coupled to the main memory primarily via a secondary bus but also via the M bus. External TAGs coupled between the M bus and the secondary bus are used to maintain coherency between the first and second processing systems. Each external TAG corresponds to a particular cache/MMU integrated circuit and maintains information as to the status of its corresponding cache/MMU integrated circuit. The cache/MMU integrated circuit provides the necessary status information to its corresponding external TAG in a very efficient manner. Each cache/MMU integrated circuit can also be converted to a SRAM mode in which the cache performs like a conventional high speed static random access memory (SRAM). This ability to convert to a SRAM provides the first processing system with a very efficient scratch pad capability. Each cache/MMU integrated circuit also provides hit information external to the cache/MMU integrated circuit with respect to transactions on the P bus. This hit information is useful in determining system performance.

Title
Cache which provides status information
Application Number
7/339464
Publication Number
5067078
Application Date
April 17, 1989
Publication Date
November 19, 1991
Inventor
James B Gullette
Austin
TX, US
James A Klingshirn
Austin
TX, US
Yoav Talgam
Tel-Aviv
IL
Agent
James L Clingan Jr
Assignee
Motorola
IL, US
IPC
G11C 8/00
G06F 7/20
G06F 7/04
G06F 7/00
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