05063172 is referenced by 54 patents and cites 7 patents.

The present invention provides an integrated circuit fabrication method that utilizes a conductive spacer to define the gate length of the series select transistor in a split-gate memory cell. Since the length of the spacer can be controlled with great precision using existing integrated circuit process technologies, misalignment problems associated with the prior art split-gate cells are eliminated.

Title
Manufacture of a split-gate EPROM cell using polysilicon spacers
Application Number
545397
Publication Number
5063172
Application Date
February 5, 1991
Publication Date
November 5, 1991
Inventor
Martin H Manley
San Jose
CA, US
Agent
Limbach Limbach & Sutton
Assignee
National Semiconductor Corporation
CA, US
IPC
H01L 21/265
View Original Source