05058048 is referenced by 140 patents and cites 6 patents.

A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When an denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent. If the result has a zero or negative exponent, the result is directed through the second arithmetic unit a second time so that the result is denormalized. The denormalized result is then output.

Title
Normalizing pipelined floating point processing unit
Application Number
7/503819
Publication Number
5058048
Application Date
April 2, 1990
Publication Date
October 15, 1991
Inventor
Brian D McMinn
Austin
TX, US
Thomas W Lynch
Austin
TX, US
Robert M Perlman
San Jose
CA, US
Smeeta Gupta
Saratoga
CA, US
Agent
Johnson & Gibbs
Assignee
Advanced Micro Devices
CA, US
IPC
G06F 7/38
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