05041886 is referenced by 94 patents and cites 3 patents.

A nonvolatile semiconductor memory device is provided including a doped semiconductor substrate and three gate conductor layers electrically insulated from each other in the cell area on the substrate. A first floating gate conductor layer is formed on the substrate and covered by a second control gate conductor layer, forming a twofold polycrystalline silicon structure. A third select gate conductor layer is formed along one side wall of the twofold structure of the floating gate and control gate conductor layers, having a side wall spacer structure. The first conductor layer serves as a floating gate; the second conductor layer serves as a control gate; and the third conductor layer serves as a select gate. A field oxide layer is provided to separate cells from each other. The control and the select gates are connected in a region between cells through the field oxide layer. By providing the third conductor in the form of a side wall spacer, the cell area can be greatly reduced.

Title
Nonvolatile semiconductor memory device and manufacturing method thereof
Application Number
7/412305
Publication Number
5041886
Application Date
September 25, 1989
Publication Date
August 20, 1991
Inventor
Soo Cheol Lee
Seoul
KR
Agent
Cushman Darby & Cushman
Assignee
Samsung Electronics
KR
IPC
H01L 29/68
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