05036298 is referenced by 19 patents and cites 2 patents.

A voltage-controlled delay is connected in series with a phase-locked loop. The voltage-controlled delay is controlled by the control voltage developed by the phase-locked loop amplifier and filter. With this arrangement, the amplifier and filter can be designed to have a transfer function that does not include an explicit zero. Consequently, the jitter transfer function of the overall structure can be designed to remain equal to or less than unity over all frequencies and jitter peaking is eliminated.

Title
Clock recovery circuit without jitter peaking
Application Number
7/514748
Publication Number
5036298
Application Date
April 26, 1990
Publication Date
July 30, 1991
Inventor
John Bulzachelli
Arlington
MA, US
Agent
Wolf Greenfield & Sacks
Assignee
Analog Devices
MA, US
IPC
H03L 7/00
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