05034337 is referenced by 168 patents and cites 17 patents.

A process of fabricating semiconductor devices involving plural epitaxial layer growth steps.

Title
Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices
Application Number
309452
Publication Number
5034337
Application Date
August 29, 1990
Publication Date
July 23, 1991
Inventor
David R Cotton
Plano
TX, US
Larry Latham
Garland
TX, US
Joe R Trogolo
Plano
TX, US
Cornelia H Blanton
Plano
TX, US
Dan M Mosher
Plano
TX, US
Agent
Melvin Sharp
James T Comfort
B Peter Barndt
Assignee
Texas Instruments Incorporated
TX, US
IPC
H01L 21/76
H01L 21/74
H01L 21/331
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