05019965 is referenced by 20 patents and cites 10 patents.

In a computer system, the flow of data from the execution unit to the cache 28 is enhanced by pairing individual, sequential longword write operations into a simultaneous quadword write operation. Primary and secondary writebuffers 50, 52 sequentially receive the individual longwords during first and second clock cycles and simultaneously present the individual longwords over a quadword wide bus to the cache 28. During the first clock cycle, when the cache 28 is not performing the quadword write operation, the cache 28 is free to perform the requisite lookup routine on the address of the first longword of data to determine if the quadword of address space is available in the cache. Thus, the flow of data to the cache 28 is maximized.

Title
Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width
Application Number
7/306826
Publication Number
5019965
Application Date
February 3, 1989
Publication Date
May 28, 1991
Inventor
Dwight P Manley
Holliston
MA, US
Trvggve Fossum
Northboro
MA, US
Ronald M Salett
Framingham
MA, US
Ricky C Hetherington
Northboro
MA, US
David A Webb Jr
Berlin
MA, US
Agent
Arnold White & Durkee
Assignee
Digital Equipment Corporation
MA, US
IPC
G06F 13/00
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