05014195 is referenced by 89 patents and cites 10 patents.

A set associative cache using decoded data element select lines which can be selectively configured to provide different data sets arrangements. The cache includes a tag array, a number of tag comparators corresponding to the maximum possible number of sets, a data element select logic circuit, and a data array. The tag and data arrays each provide, in response to an input address, a number of output tag and data elements, respectively. The number of output tag and data elements depends upon the maximum set size desired for the cache. An input main memory address is used to address both the tag and data arrays. The tag comparators compare a tag field portion of the input main memory address to each element output from the tag array. The select logic then uses the outputs of the tag comparators and one or more of the input main memory address bits to generate decoded data array enable signals. The decoded enable signals are then coupled to enable the desired one of the enabled data elements.

Title
Configurable set associative cache with decoded data element enable lines
Application Number
7/522503
Publication Number
5014195
Application Date
May 10, 1990
Publication Date
May 7, 1991
Inventor
Richard L Sites
Boylston
MA, US
James A Farrell
Marlboro
MA, US
Agent
Cesari and McKenna
Assignee
Digital Equipment Corporation
MA, US
IPC
G11C 13/00
View Original Source