05003463 is referenced by 57 patents and cites 18 patents.

An information processing system comprises a high speed noninterlocked system bus 12 which couples together a plurality of system units including a main memory and a system bus interface (SBI) unit 34. The system bus interface unit is further coupled to an I/O bus 42 having a plurallity of I/O Processors 44, 46 coupled thereto. The system bus interface includes read and write buffer storage for buffering information units being transferred between the system bus and the I/O bus. The I/O bus includes two signal lines which differentiate the condition of an I/O bus SBI BUSY signal line. One of these two signal lines indicates when the SBI read buffer is full while the other signal line indicates when the SBI write buffer is full. The SBI Busy signal line indicates when either of these conditions exist. I/O processors are enabled to differentiate between read and write buffer full conditions, thereby effectively increasing the bandwidth of the I/O bus.

Title
Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus
Application Number
7/213401
Publication Number
5003463
Application Date
June 30, 1988
Publication Date
March 26, 1991
Inventor
Thomas B Berg
West Lafayette
IN, US
Zenja Chao
North Andover
MA, US
Richard W Coyle
Dunstable
MA, US
Agent
Michael H Shanahan
Assignee
Wang Laboratories
MA, US
IPC
G06F 15/16
G06F 13/12
G06F 13/00
G06F 3/00
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