04999813 is referenced by 41 patents and cites 5 patents.

In a nonvolatile semiconductor memory, a plurality of nonvolatile semiconductor memory cells are arranged in a matrix form. Each of the memory cells is connected to a corresponding one of a plurality of bit lines and to a corresponding one of a plurality of word lines. The ends of the bit lines are commonly connected to a programming transistor for setting a programming mode through transistors for selecting the bit lines. The transistors are connected to column decoders and the word lines are connected to a row decoder. Furthermore, the other ends of the bit lines are connected to a common connecting line through transistors for setting a test mode and the common connecting line is connected to a node between the test mode transistors and a series circuit of a transistor and a dummy memory cell in a clamp circuit. The transistor of the clamp circuit is connected to a high voltage and the series circuit is connected to the ground. In the test mode, the programming transistor and the bit line selecting transistors are turned off and the test mode transistors and the transistor connected to the clamp circuit are turned on. Thus, a test voltage is applied to the memory cells through the common connecting line, the test mode transistors and the bit lines.

Title
Nonvolatile semiconductor memory having a stress test circuit
Application Number
261863
Publication Number
4999813
Application Date
April 20, 1989
Publication Date
March 12, 1991
Inventor
Shigeru Atsumi
Tokyo
JP
Junichi Miyamoto
Yokohama
JP
Nobuaki Ohtsuka
Yokohama
JP
Agent
Finnegan Henderson Farabow Garrett and Dunner
Assignee
Kabushiki Kaisha Toshiba
JP
IPC
G11C 16/04
G11C 29/00
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