04995041 is referenced by 47 patents and cites 6 patents.

In the operation of high-speed computers, it is frequently advantageous to employ a high speed cache memory within each CPU of a multiple CPU computer system. A standard, slower memory configuration remains in use for the large, common main memory, but those portions of main memory which are expected to be used heavily are copied into the cache memory. Thus, on many memory references, the faster cache memory is exploited, while only infrequent references to the slower main memory are necessary. This configuration generally speeds the overall operation of the computer system; however, memory integrity problems arise by maintaining two separate copies of selected portions of main memory. Accordingly, the memory access unit of the CPU uses error correction code (ECC) hardware to ensure the integrity of the data delivered between the cache and main memory. The prevent the ECC hardware from slowing the overall operation of the CPU, the error correction is performed underneath a write back operation. Data contained in the cache, which will be displaced by data received from main memory 10, is transferred to a write back buffer (WBB) during that period of time between the request for data from the main memory and actual delivery of the requested data. Further, the ECC hardware also operates on the cache data being written to the WBB. Accordingly, a performance penalty is avoided by performing error correction and preremoving the cache data during that idle period of time.

Title
Write back buffer with error correcting capabilities
Application Number
7/306703
Publication Number
4995041
Application Date
February 3, 1989
Publication Date
February 19, 1991
Inventor
David A Webb Jr
Berlin
MA, US
Maurice B Steinman
Grafton
MA, US
Tryggve Fossum
Northboro
MA, US
Ricky C Hetherington
Northboro
MA, US
Agent
Arnold White & Durkee
Assignee
Digital Equipment Corporation
MA, US
IPC
G06F 11/10
View Original Source