04985848 is referenced by 200 patents and cites 105 patents.

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116).

Title
High speed image processing system using separate data processor and address generator
Application Number
7/97664
Publication Number
4985848
Application Date
September 14, 1987
Publication Date
January 15, 1991
Inventor
Michael K Corry
Dallas
TX, US
James A Fontaine
Plano
TX, US
Jay A Thompson
Plano
TX, US
Dwight D Dipert
Richardson
TX, US
John P Norsworthy
Carrollton
TX, US
David T Stoner
McKinney
TX, US
David M Pfeiffer
Plano
TX, US
Agent
Baker & Botts
Assignee
Visual Information Technologies
TX, US
IPC
G06F 15/20
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