04985825 is referenced by 77 patents and cites 7 patents.

A technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed. In response to the detection of access exceptions at a pipeline stage, corresponding fault information is generated and transferred along the pipeline. The fault information is acted upon only when the instruction reaches the execution stage of the pipeline. Each stage of the instruction pipeline is ported into the front end of a memory unit adapted to perform the virtual-to-physical address translation; each port being provided with storage for virtual addresses accompanying an instruction as well as storage for corresponding fault information. When a memory access exception is encountered at the front end of the memory unit, the fault information generated therefrom is loaded into the storage and the port is prevented from accepting further references.

Title
System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer
Application Number
7/306866
Publication Number
4985825
Application Date
February 3, 1989
Publication Date
January 15, 1991
Inventor
Tryggve Fossum
Northboro
MA, US
Ronald M Salett
Framingham
MA, US
Dwight P Manley
Holliston
MA, US
John E Murray
Acton
MA, US
Mark A Firstenberg
Maynard
MA, US
Francis X McKeen
Westboro
MA, US
Ricky C Hetherington
Northboro
MA, US
David B Fite
Northboro
MA, US
David A Webb Jr
Berlin
MA, US
Agent
Arnold White & Durkee
Assignee
Digital Equipment Corporation
MA, US
IPC
G06F 12/10
G06F 11/30
G06F 9/38
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