04979145 is referenced by 24 patents and cites 11 patents.

A dynamic random access memory has a bit of data selected by a multiplexed address. The row address latches twice as much data as can be selected by the column address which follows the row address. After the column address has been utilized, there is still a one of two selection between two bits of data required. One of the row addresses provides the final selection between the two bits of data. An array toggle signal available from an extra pin is used to switch the state of the internal signal which corresponds to the one row address signal which makes the final one of two selection. The array toggle signal thus makes it possible to access any of the latched data in a high speed mode in which only the column address is changed to select among the bits of data which are already latched.

Title
Structure and method for improving high speed data rate in a DRAM
Application Number
6/858326
Publication Number
4979145
Application Date
May 1, 1986
Publication Date
December 18, 1990
Inventor
William L Martino Jr
Austin
TX, US
Scott Remington
Austin
TX, US
Agent
James L Clingan Jr
Assignee
Motorola
IL, US
IPC
G06F 12/06
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