04967339 is referenced by 10 patents and cites 7 patents.

A processor performs a pipelined parallel processing by an operand effective address calculation unit for calculating an operand effective address necessary to execute an instruction and an instruction execution unit for executing the instruction. A 64 bit width data operation is performed in such a way that a high order 32 bit operation is performed in an arithmetic device in the operand effective address unit and a low order 32 bit operation is performed in another arithmetic device in the instruction execution unit. A carry is transferred from the low order 32 bit arithmetic device to the high order 32 bit arithmetic device. The arithmetic devices thus joined can perform the 64 bit with data operation as an arithmetic device.

Title
Operation control apparatus for a processor having a plurality of arithmetic devices
Application Number
7/179554
Publication Number
4967339
Application Date
April 8, 1988
Publication Date
October 30, 1990
Inventor
Kenji Hirose
Hitachi
JP
Shinichiro Yamaguchi
Hitachi
JP
Tadaaki Bandoh
Ibaraki
JP
Takayuki Morioka
Hitachi
JP
Soichi Takaya
Hitachi
JP
Hiroaki Fukumaru
Hitachi
JP
Agent
Antonelli Terry Stout & Kraus
Assignee
Hitachi Engineering
JP
Hitachi
JP
IPC
G06F 7/00
G06F 12/00
G06F 9/30
G06F 9/38
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