04965828 is referenced by 75 patents and cites 23 patents.

A non-volatile memory system includes an SRAM and a backup store of E.sup.2 PROMs. In the event of a short duration power interruption, the memory system enters a hold mode in which data maintenance power is supplied to the SRAM by discharging a backup capacitor, and accessing of the SRAM by a host computer is halted. If the backup capacitor voltage does not fall below a threshold before power is restored, the hold mode is terminated and accessing by the host computer continues. If the backup capacitor voltage falls below the threshold, operating power is supplied to the SRAM, E.sup.2 PROM, and associated circuitry to download all data and row and column parity data into the E.sup.2 PROM by further discharging of the backup capacitor. Row parity and column parity information are accumulated by a bit-per-chip accumulation technique that allows convenient error correction on a "per chip" basis. Data is encrypted and decrypted on the basis of a fully erasable magnetic key.

Title
Non-volatile semiconductor memory with SCRAM hold cycle prior to SCRAM-to-E.sup.2 PROM backup transfer
Application Number
7/333709
Publication Number
4965828
Application Date
April 5, 1989
Publication Date
October 23, 1990
Inventor
Sam L Rainwater
Tempe
AZ, US
Robert E Peters
Tempe
AZ, US
John F Bruder
Phoenix
AZ, US
Harold L Ergott Jr
Fountain Hills
AZ, US
Agent
Cahill Sutton & Thomas
Assignee
Quadri Corporation
AZ, US
IPC
G11B 23/28
H04L 9/00
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