04965717 is referenced by 169 patents and cites 12 patents.

A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. Memory references. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references by the multiple CPUs are voted by each of the memory modules. A private-write area is included in the shared memory space in the memory modules to allow functions such as software voting of state information unique to CPUs. All CPUs write state information to their private-write area, then all CPUs read all the private-write areas for functions such as detecting differences in interrupt cause or the like.

Title
Multiple processor system having shared memory with private-write capability
Application Number
7/283573
Publication Number
4965717
Application Date
December 13, 1988
Publication Date
October 23, 1990
Inventor
Douglas E Jewett
Austin
TX, US
Nikhil A Mehta
Austin
TX, US
Richard W Cutts Jr
Georgetown
TX, US
Agent
Arnold White & Durkee
Assignee
Tandem Computers Incorporated
CA, US
IPC
G06F 15/16
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