04963504 is referenced by 81 patents and cites 2 patents.

An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment member and a heavily doped junction is aligned with the outboard alignment members.

Title
Method for fabricating double implanted LDD transistor self-aligned with gate
Application Number
123693
Publication Number
4963504
Application Date
November 24, 1989
Publication Date
October 16, 1990
Inventor
Tiao Yuan Huang
Cupertino
CA, US
Agent
Serge Abend
Assignee
Xerox Corporation
CT, US
IPC
H01L 21/265
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