04945511 is referenced by 20 patents and cites 3 patents.

A pipelined processor to improve the efficiency of conventional pipelined instruction processing including a two stage instruction decoder which converts sets of similar conventional instructions having the general formats: "MOV: A R1 R2" and "MOV: B R1 R2" where the letter fields A,B etc. indicate the direction of data transfer between the registers, R1, R2; into a single format instruction which can be processed by one microprogram. The first stage decoder processes one instruction intact and generates an intermediate code for the remaining format instruction. The second stage decoder utilizes the intermediate code to specify the direction of transfer by reversing the sequence of register numbers in the instruction not processed intact by the first stage. The resulting transfer instructions have the same format and thus require one, rather than two, microprograms for execution, making the pipelined processor more efficient.

Title
Improved pipelined processor with two stage decoder for exchanging register values for similar operand instructions
Application Number
7/371961
Publication Number
4945511
Application Date
June 27, 1989
Publication Date
July 31, 1990
Inventor
Toyohiko Yoshida
Itami
JP
Fujio Itomitsu
Itami
JP
Agent
Townsend and Townsend
Assignee
Mitsubishi Denki Kabushiki Kaisha
JP
IPC
G06F 9/00
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