04933835 is referenced by 95 patents and cites 75 patents.

A microprocessor system is disclosed having a high speed system bus for coupling system elements, and having a dual bus microprocessor with separate ultra-high speed instruction and data cache-MMU interfaces coupled to independently operable instruction and data cache-MMU, respectively. A main memory is coupled to the system bus for selectively storing and outputting digital information. The instruction and data cache-MMU's are coupled to the main memory via the system bus for independently storing and outputting digital information to respective mapped addressable very high speed cache memory. The microprocessor is coupled via separate and independent very high speed instruction and data buses to each of the instruction cache-MMU and data cache-MMU, respectively, for processing data received from the data cache-MMU responsive to instructions received from the instruction cache-MMU. The instruction bus and data bus are exclusive and independent of one another, and allow for simultaneous very high-speed transfer. The data cache-MMU and instruction cache-MMU each have separate dedicated system bus interfaces for coupling to the main memory and to other peripheral devices which are coupled to the system bus. Numerous other system elements can also be coupled to the system bus, including an interrupt controller, an I/O processor, a bus arbiter, an array processor, and other peripheral controller devices.

Title
Apparatus for maintaining consistency of a cache memory with a primary memory
Application Number
704568
Publication Number
4933835
Application Date
January 19, 1989
Publication Date
June 12, 1990
Inventor
Walter H Hollingsworth
Campbell
CA, US
James Y Cho
Los Gatos
CA, US
Howard G Sachs
Los Altos
CA, US
Agent
Townsend and Townsend
Assignee
Intergraph Corporation
AL, US
IPC
G06F 9/00
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