04918614 is referenced by 156 patents and cites 5 patents.

A system in which logic and/or memory elements are automatically placed on an integrated circuit ("floorplanning") taking into account the constraints imposed by the logic designer, not only increase the density of the integrated circuit, and the likelihood of routing interconnections among the elements on that circuit, but it also enables the user to quickly modify the floorplan manually, and then graphically display the results of such modifications. By conforming itself to the logic designer's modular, hierarchical design, the system is capable of placing elements at each level of the specified hierarchy, based upon the number of interconnections between elements throughout that hierarchy. The system includes means for estimating the size of elements which have not yet been laid out, and for partitioning groups of elements into successively smaller "slices" of the integrated circuit (using heuristic techniques when exhaustive methods are no longer feasible) until all elements are placed relative to one another. The system also includes means for determining the precise shapes of elements on the integrated circuit, based upon the relative placement of such elements, and upon the additional area required for routing interconnections among such elements. The functionality of this hierarchical floorplanning system can be embodied in the form of software, hardware or any combination thereof, because the system's hierarchical methodology and structure is independent of its particular embodiment.

Title
Hierarchical floorplanner
Application Number
7/57843
Publication Number
4918614
Application Date
June 2, 1987
Publication Date
April 17, 1990
Inventor
Jiun Hao Lai
Santa Clara
CA, US
Susan Raam
Fremont
CA, US
Hossein Modarres
Mountain View
CA, US
Agent
Skjerven Morrill MacPherson Franklin & Friel
Assignee
LSI Logic Corporation
CA, US
IPC
G06F 15/60
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