04912540 is referenced by 10 patents and cites 6 patents.

A reduced area butting contact structure (10') is provided, which is especially suited for four-transistor static RAM cells. A structure is formed which includes a doped silicon region and one or more layers of polysilicon and oxide situated thereabove, one of which layers of polysilicon may be a gate polysilicon. An anisotropic etch is then performed through all upper layers including any upper polysilicon layers which may be present, but stopping at the doped silicon region and any gate polysilicon layers present, to form a contact hole (26'). The contact hole is filled with a conductive plug (32) of a material such as tungsten or polysilicon and etched back. In either case, contact with all polysilicon layers present and the doped silicon region is made. In the anisotropic etching process, a two-step etch is employed. The first etch is non-specific as to material, etching all relevant materials (polysilicon and oxide) at substantially the same rate and is continued through any upper polysilicon layers, but is terminated prior to etching the doped silicon region or any gate polysilicon layers (22). The second etch is specific as to material, etching silicon dioxide faster than polysilicon or silicon, and thus stops at the gate polysilicon layer and the doped silicon region.

Title
Reduced area butting contact structure
Application Number
944150
Publication Number
4912540
Application Date
August 5, 1988
Publication Date
March 27, 1990
Inventor
Tat C Choi
Milpitas
CA, US
Richard K Klein
Mountain View
CA, US
Craig S Sander
Mountain View
CA, US
Agent
Ashen Golant Martin & Selden
Assignee
Advanced Micro Devices
CA, US
IPC
H01L 29/34
H01L 23/48
H01L 29/04
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