04912345 is referenced by 116 patents and cites 3 patents.

A programmable logic device includes a programmable logic array and an output logic macrocell. The output logic macrocell includes a user configurable summing function that has a first logic gate connected to receive a first plurality of product terms, a second logic gate connected to receive a second plurality of product terms and a third logic gate connected to receive the combination of the first plurality of product terms and a controls signal, a fourth logic gate connected to receive the combination of the second plurality of Product Terms and the control signal and a logic circuit connected to receive the output signals from the first, second, third and fourth logic gates and to provide a first logical combination when the control signal is at a first logic state and a second logical combination when the controls signal is at a second logic state.

Title
Programmable summing functions for programmable logic devices
Application Number
7/291711
Publication Number
4912345
Application Date
December 29, 1988
Publication Date
March 27, 1990
Inventor
Safoin A Raad
Scottsdale
AZ, US
Randy C Steele
Scottsdale
AZ, US
Agent
Kenneth C Hill
Richard K Robinson
Assignee
SGS Thomson Microelectronics
TX, US
IPC
H03K 19/094
H03K 19/173
View Original Source