04910656 is referenced by 26 patents and cites 11 patents.

A data processing system having a bus master, a cache, and a memory which is capable of transferring operands in bursts in response to a burst request signal provided by the bus master. The bus master will provide the burst request signal to the memory in order to fill a line in the cache only if there are no valid entries in that cache line. If a requested operand spans two cache lines, the bus master will defer the burst request signal until the end of the transfer of that operand, so that only the second cache line will be burst filled.

Title
Bus master having selective burst initiation
Application Number
7/99366
Publication Number
4910656
Application Date
September 21, 1987
Publication Date
March 20, 1990
Inventor
William D Wilson
Redwood City
CA, US
William C Moyer
Dripping Springs
TX, US
Hunter L Scales III
Austin
TX, US
Agent
Robert L King
Assignee
Motorola
IL, US
IPC
G06F 13/28
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