04905143 is referenced by 53 patents and cites 24 patents.

An array processor comprising multiplexers, plural processing elements connected through the multiplexers in the form of a ring and a control unit for controlling the multiplexers and the processing elements. Each of the processing elements is connected to an input vector data bus via the multiplexer and directly to an I/O data bus, so that two types of input vector data are inputted to the processing element simultaneously. Flags indicating a position of respective vector data are added to each one of input vector data, series composed of a combination of plural types of input vector data series. The processing element judges a processing status of the processing element to control a selection of the input vector data bus or the transfer path, data transfer between the processing elements, or data input/output to/from the I/O bus, so that the overall array processor executes autonomous control of all the combinations of the vector data of the two types of input vector data series. The array processor realizes parallel processing of pattern matching computation based upon dynamic time warping with a high efficiency and thus realizes a highefficiency utilization of hardware resources including processing elements and network.

Title
Array processor and control method thereof
Application Number
705376
Publication Number
4905143
Application Date
June 14, 1988
Publication Date
February 27, 1990
Inventor
Atsushi Iwata
Kanagawa
JP
Takashi Kimura
Kanagawa
JP
Sanshiro Hattori
Kanagawa
JP
Junichi Takahashi
Kanagawa
JP
Agent
Cushman Darby & Cushman
Assignee
Nippon Telegraph and Telephone Public Company
JP
IPC
G06F 15/00
G06F 15/16
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