04903196 is referenced by 137 patents and cites 12 patents.

A method and apparatus for controlling access to its general purpose registers (GPRs) by a high end machine configuration including a plurality of execution units within a single CPU. The invention allows up to "N" execution units to be concurrently executing up to "N" instructions using the GPR sequentially or different GPR's concurrently as either SINK or SOURCE while at the same time preserving the logical integrity of the data supplied to the execution units. The use of the invention allows a higher degree of parallelism in the execution of the instructions than would otherwise be possible if only sequential operations were performed.

A series of special purpose tags are associated with each GPR and execution unit. These tags are used together with control circuitry both within the GPR's, within the individual execution units and within the instruction decode unit, which permit the multiple use of the registers to be accomplished while maintaining the requisite logical integrity.

Title
Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor
Application Number
6/859156
Publication Number
4903196
Application Date
May 2, 1986
Publication Date
February 20, 1990
Inventor
Frank J Sparacio
North Bergen
NJ, US
Rudolph N Rechtschaffen
Scarsdale
NY, US
Thomas R Puzak
Cary
NC, US
James H Pomerene
Chappaqua
NY, US
Agent
Roy R Schlemmer Jr
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 15/00
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