04901228 is referenced by 53 patents and cites 12 patents.

A cache memory includes an address back-up register for storing the physical address of the data where errors are generated for backing up the address register, a data array address back-up register for storing data address of the data where errors are generated for backing up the data array address register, and a request code back-up register for storing a preceding request code at the time of the error generation. When an error is detected by the system controller, data is read from the main memory according to the back-up registers and the control register, EYCY register and PSEDO ACK register, of the system controller.

Title
Pipelined cache system using back up address registers for providing error recovery while continuing pipeline processing
Application Number
7/73513
Publication Number
4901228
Application Date
July 15, 1987
Publication Date
February 13, 1990
Inventor
Takashi Kodama
Kamakura
JP
Agent
Kanesake & Takeuchi
Assignee
Mitsubishi Denki
JP
IPC
G06F 11/14
G06F 13/36
G06F 9/38
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