04895810 is referenced by 52 patents and cites 26 patents.

A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 --SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.

Title
Iopographic pattern delineated power mosfet with profile tailored recessed source
Application Number
842771
Publication Number
4895810
Application Date
May 17, 1988
Publication Date
January 23, 1990
Inventor
Theodore G Hollinger
Redmond
OR, US
Douglas A Pike Jr
Bend
OR, US
John W Mosier II
Bend
OR, US
Theodore O Meyer
Bend
OR, US
Agent
Marger & Johnson
Assignee
Advanced Power Technology
OR, US
IPC
H01L 21/467
View Original Source