04894706 is referenced by 67 patents and cites 15 patents.

A chip carrying member (1) such as a film carrier carrying a chip (10) and elastic spacers (2, 3) are stacked to form an elementary unit with adjusting its thickness. By using an aligning aperture (12) of a thin sheet (1), a plurality of the elementary units are stacked to form a laminated structure. From a side surface of the laminated structure, leads (13) are extended to be connected to a wiring board (241), or after the leads (13) are buried in an insulator (8), the leads (13) and insulator (8) are abraded to form a coplanar surface and then a wiring layer (82) for interconnecting is formed on the abraded surface. A usual chip can be mounted on the chip carrying member (1) without any work with a high accuracy in alignment of the lamination and furthermore with a high accuracy in a lamination pitch of the chip carrying member (1), so that the leads (13) of the chip (10) can be wired precisely and finely. A low cost and high density three-dimensional packaging structure can be realized.

Title
Three-dimensional packaging of semiconductor device chips
Application Number
6/919001
Publication Number
4894706
Application Date
October 9, 1986
Publication Date
January 16, 1990
Inventor
Katsuhiko Aoki
Tokyo
JP
Masanobu Oohata
Atsugi
JP
Kunio Koyabu
Tokyo
JP
Junji Watanabe
Tokyo
JP
Kazuhide Kiuchi
Atsugi
JP
Yoshiyuki Sato
Atsugi
JP
Agent
Spencer & Frank
Assignee
Nippon Telegraph and Telephone Corporation
JP
IPC
H01L 23/28
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