04890153 is referenced by 37 patents.

An integrated circuit assembly (10) includes a bipolar VLSI die (12) contained in a multilayer ceramic pin-grid array package (14). A bonding shelf (18) defined on a single ceramic layer contains an inner row (20) of bonding pads (26) and an outer row (22) of bonding pads (28). Bonding wires (30, 32) extend from bonding pads (34) on the die to the opposing pads on the inner and outer rows to provide an electrical interface between the die and the package. The inner and outer bonding pads are connected by metallized fingers to conductive pads (61, 65) which provide a power and signal interface with an incorporating system.

The inner pads include metallized vias (24) to metallized segments on a layer other than that on which the bonding shelf is defined. Thus, the metallized fingers including the inner row of pads can extend to the pins while passing above or below, rather than between, adjacent pads of the outer row. In this way, the pitch of the package bonding pads is effectively doubled without the misalignment, and resulting problems with shorted bonding wires, inherent when the rows are located on separated bonding shelves.

Title
Single bonding shelf, multi-row wire-bond finger layout for integrated circuit package
Application Number
7/848302
Publication Number
4890153
Application Date
April 4, 1986
Publication Date
December 26, 1989
Inventor
Ching An Wu
San Jose
CA, US
Agent
Clifton L Anderson
Lee Patch
Assignee
Fairchild Semiconductor Corporation
CA, US
IPC
H04N 9/16
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